Package description for 'iverilog'

Icarus Verilog

 Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
 compiler, compiling source code writen in Verilog (IEEE-1364) into some target
 format. For batch simulation, the compiler can generate an intermediate form
 called vvp assembly. This intermediate form is executed by the ``vvp'' command.
 For synthesis, the compiler generates netlists in the desired format.

Various other information for package 'iverilog'   (Repository 'clifford')

URL: https://www.icarus.com/eda/verilog/

Author: Stephen Williams
Maintainer: Clifford Wolf <clifford@clifford.at>

License: GPL
Status: Stable
Version: 0.8.6

Download: ftp://icarus.com/pub/eda/verilog/v0.8/ verilog-0.8.6.tar.gz

Buildtime: 20472 (5) seconds (on reference hardware)
Buildtime: 21473 (9) seconds (on reference hardware)
Package Size: 2.00 MB, 33 files

Dependencies: 00-dirtree bash2 binutils bison bzip2 bzip2:dev coreutils cvm
Dependencies: diffutils findutils flex gawk gcc42 gcc42:dev glibc26 glibc26:dev
Dependencies: grep linux26-headers:dev ltrace m4 make mktemp ncurses net-tools
Dependencies: readline readline:dev sed sysfiles tar util-linux xmame zlib zlib:dev

ROCK Sources:  hotfixes.patch,  iverilog.cache,  iverilog.conf,  iverilog.desc